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| author | Gabriel Wicki <gabriel@erlikon.ch> | 2026-01-15 16:39:07 +0100 |
|---|---|---|
| committer | Cayetano Santos <csantosb@inventati.org> | 2026-03-06 09:42:34 +0100 |
| commit | 1ae39621d29e574dd31f71592fbdf7ce40adcb28 (patch) | |
| tree | 9b3e4ac9f406ede749e9c80957267d2437427bec /gnu/packages | |
| parent | d1f4adcd1caa39f00efc63cb280f5dcae0968884 (diff) | |
gnu: Add librelane.
* gnu/packages/electronics.scm (librelane): New variable.
Merges guix/guix!5641
Change-Id: Ic66549a02671e6315233075fb60a5bd7af93f398
Signed-off-by: Cayetano Santos <csantosb@inventati.org>
Diffstat (limited to 'gnu/packages')
| -rw-r--r-- | gnu/packages/electronics.scm | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm index f07253afb63..e276953a2ae 100644 --- a/gnu/packages/electronics.scm +++ b/gnu/packages/electronics.scm @@ -1059,6 +1059,61 @@ an embedded event driven algorithm.") license:bsd-3 ;ciderlib license:public-domain)))) ;xspice +(define-public librelane + (package + (name "librelane") + (version "3.0.0rc0") + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/librelane/librelane") + (commit version))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1hi4ppdwl1zh7yw1ncy1jrqc6za4mz243mqvfjr7mcdm349pyvb0")))) + (build-system pyproject-build-system) + (arguments + (list + #:phases + #~(modify-phases %standard-phases + (add-before 'build 'fix-build + (lambda* (#:key inputs #:allow-other-keys) + (substitute* "librelane/steps/verilator.py" + (("\"verilator\"") + (format #f "~s" + (search-input-file inputs "/bin/verilator"))))))))) + (native-inputs + (list python-customtkinter + python-poetry-core + python-pyfakefs + python-pytest + python-setuptools)) + (inputs + (list ciel + python-click + python-cloup + python-deprecated + python-httpx + python-klayout + python-lln-libparse + python-lxml + python-pcpp + python-psutil + python-pyyaml + python-rapidfuzz + python-rich + python-semver + python-yamlcore-0.0.2 + verilator)) + (home-page "https://librelane.readthedocs.io/") + (synopsis "ASIC implementation flow infrastructure") + (description "LibreLane is an @acronym{EDA, Electronic Design Automation} +ASIC infrastructure library based on several components including OpenROAD, +Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design +exploration and optimization.") + (license license:asl2.0))) + (define-public librepcb (package (name "librepcb") |