diff options
| author | Cayetano Santos <csantosb@inventati.org> | 2026-01-17 10:24:32 +0100 |
|---|---|---|
| committer | Rutherther <rutherther@ditigal.xyz> | 2026-01-25 21:24:47 +0100 |
| commit | b9f0fd3317b165136a588ca9397fa4c7fc44f337 (patch) | |
| tree | 35774903421389dfb783576afb62044fb45dbb7b /gnu/packages/electronics.scm | |
| parent | 668a75caddee8c36d9babcc47ab3a88601eb1d1a (diff) | |
gnu: verilator: Update to 5.044.
* gnu/packages/electronics.scm (verilator): Update to 5.044.
[synopsis]: Complete.
[description]: Update.
Change-Id: I01d14696c52e519817ec827fbabcc0d36f3e0d80
Signed-off-by: Rutherther <rutherther@ditigal.xyz>
Diffstat (limited to 'gnu/packages/electronics.scm')
| -rw-r--r-- | gnu/packages/electronics.scm | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm index 3c5dae1b80f..8b84642cb2d 100644 --- a/gnu/packages/electronics.scm +++ b/gnu/packages/electronics.scm @@ -3566,7 +3566,7 @@ unique design feature of Trilinos is its focus on packages.") (define-public verilator (package (name "verilator") - (version "5.042") + (version "5.044") (source (origin (method git-fetch) @@ -3575,7 +3575,7 @@ unique design feature of Trilinos is its focus on packages.") (commit (string-append "v" version)))) (file-name (git-file-name name version)) (sha256 - (base32 "0md5ngfl59xrccbfrz9dn1803n641cz37i4mmpwapx1nvqxfl5zs")))) + (base32 "1x6c94phxjsl5d54rg6bf8ylswsq8729l6rhf2lf6rv770vxhy6g")))) (native-inputs (list autoconf automake @@ -3614,11 +3614,12 @@ unique design feature of Trilinos is its focus on packages.") (display "set auto-load safe-path /")))))) #:test-target "test")) (home-page "https://www.veripool.org/verilator/") - (synopsis "Verilog/SystemVerilog simulator") + (synopsis "Verilog/SystemVerilog HDL simulator and lint system") (description - "Verilator transforms the specified Verilog or SystemVerilog code by + "Verilator is an @acronym{EDA, Electronic Design Automation} tool +intended to transform the specified Verilog or SystemVerilog HDL code by reading it, performing lint checks, and optionally inserting assertion checks -and coverage-analysis points. It outputs single- or multi-threaded +and coverage-analysis points. It outputs single or multi-threaded @file{.cpp} and @file{.h} files.") (license license:lgpl3))) |