From 6c59ea3e9a3fb07a9661a9b72b2aa2a7ac8e66ec Mon Sep 17 00:00:00 2001
From: Cayetano Santos <csantosb@inventati.org>
Date: Sun, 1 Mar 2026 19:52:34 +0100
Subject: gnu: netgen: Improve style.

* gnu/packages/electronics.scm (netgen): Limit max column.
[arguments]<#:make-flgas>: Add.
[inputs]: Add libx11, libxt, and readline.
[synopsis]: Improve.
[description]: Improve.

Change-Id: I67fd7a336e9e989de77db57bbd120df827614349
---
 gnu/packages/electronics.scm | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

(limited to 'gnu')

diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm
index 25b345a72b9..a67bf71286d 100644
--- a/gnu/packages/electronics.scm
+++ b/gnu/packages/electronics.scm
@@ -1595,19 +1595,21 @@ coverage.")
     (arguments
      (list
       #:tests? #f ; no tests
+      #:make-flags #~(list (string-append "CC=" #$(cc-for-target))
+                           (string-append "PREFIX=" #$output))
       #:configure-flags
-      #~(list (string-append
-               "--with-tcl=" #$(this-package-input "tcl"))
-              (string-append
-               "--with-tk=" #$(this-package-input "tk")))))
-    (inputs (list tcl tk))
+      #~(list (string-append "--with-tcl=" #$(this-package-input "tcl"))
+              (string-append "--with-tk=" #$(this-package-input "tk")))))
+    (inputs (list libx11 libxt readline tcl tk))
     (native-inputs (list python-minimal-wrapper))
     (home-page "http://opencircuitdesign.com/netgen/")
-    (synopsis "@acronym{LVS, layout versus schematic} tool for comparing SPICE or verilog netlists")
-    (description "@code{netgen} compares netlists of circuits. This is commonly used as a part of
-@acronym{EDA, electronic design automation} toolchains in a
-process called @acronym{LVS, layout versus schematic} with the intent to verify
-that the layout of a circuit corresponds to the desired netlists.")
+    (synopsis "Netlist system for @acronym{EDA, electronic design automation}")
+    (description
+     "@code{netgen} is a general purpose @acronym{LVS, layout versus
+schematic} management tool.  It compares netlists of SPICE or verilog netlists
+circuits. This is commonly used as a part of toolchains in a process called
+@acronym{LVS, layout versus schematic} with the intent to verify that the
+layout of a circuit corresponds to the desired netlists.")
     (license license:gpl1)))
     
 (define-public nextpnr
-- 
cgit v1.3